1. Field of the Invention
The present invention relates to a driving method and a driving circuit for a plasma display panel to be used as flat televisions, information displays or the like, and more particularly to a driving method and a driving circuit for a plasma display panel in a reduced addressing period.
2. Description of the Related Art
In general, a plasma display panel has a number of advantages. That is, the panel features low profiles, quick response, eliminated screen flicker, and high display contrast. In addition, the panel can provide a comparatively large screen and spontaneous emission of light or multicolored light using phosphor materials.
Recently, these features allow the plasma display panel to have widespread use in the field of the computer-related display device, the color-picture display and the like.
The plasma display is divided into two types depending on the operating method. One is an AC plasma display in which the electrodes are coated with a dielectric layer and indirectly operated with alternating current discharges. The other is a DC plasma display in which the electrodes are exposed in a discharge space and operated with direct current discharges. The AC plasma display is further divided into two types. One is a memory-operated plasma display, which employs the memory of discharge cells, and the other is a non-memory-operated (refresh) plasma display. Incidentally, the luminance of the plasma display is proportional to the number of discharges. The plasma display of the aforementioned refresh type decreases in luminance with increase in capacity of display and is therefore employed for a plasma display small in capacity.
FIG. 1 is a perspective view illustrating an example of the structure of a display cell constituting an AC plasma display.
The display cell is provided with two insulating substrates 101, 102, which are made of glass. The insulating substrate 101 is a rear substrate and the insulating substrate 102 is a front substrate.
On the surface of the insulating substrate 102 opposed to the insulating substrate 101, there are provided transparent scan electrodes 103 and transparent common electrodes 104. The scan electrode 103 and common electrode 104 extend in the horizontal (lateral) direction of the panel. In addition, trace electrodes 105, 106 are disposed in overlapping relation with the scan electrode 103 and common electrode 104, respectively. For example, the trace electrodes 105, 106 are made of metal and provided to reduce the electrode resistance between each of the electrodes and an external driving unit. There are also provided a dielectric layer 112 for covering the scan electrode 103 and common electrode 104, and a protective layer 114 made of magnesium oxide for protecting the dielectric layer 112 from a discharge.
On the surface of the insulating substrate 101 opposed to the insulating substrate 102, there are provided data electrodes 107 orthogonal to the scan electrode 103 and common electrode 104. The data electrode 107 thus extends in the vertical (transverse) direction of the panel. In addition, there are provided bulkheads 109 for defining the display cells in the horizontal direction. Moreover, there are provided a dielectric layer 113 for covering the data electrode 107 and phosphor layers 111 for converting to visible light 110 an ultraviolet radiation, which is generated by discharge of a discharge gas on the side of the bulkheads 109, and the surface of the dielectric layer 113. In addition, a discharge gas space 108 is defined by the bulkheads 109 in the gap defined by the insulating substrates 101, 102. In this discharge gas space 108, filled is a discharge gas such as helium, neon, or xenon, or a mixture of these gases.
FIG. 2 is a schematic diagram illustrating the arrangement of the electrodes of the AC plasma display panel.
There are provided light-emitting display cells at the intersections of the scan electrodes S1-Sn (103) and common electrodes C1–Cn (104), disposed in parallel spaced relation to one another, and the data electrodes D1–Dm (107) disposed in orthogonal relation to the scan and common electrodes. Accordingly, one display cell is provided with one scan electrode, one common electrode, and one data electrode. Thus, the screen has the total number of (n×m) display cells, where n is the number of the scan electrodes and common electrodes, and m is the number of the data electrodes.
Now, the writing-selective-type driving operation will be explained below, which is employed by a conventional plasma display configured as described above. FIG. 3 is a timing chart illustrating the writing-selective-type driving operation for the conventional plasma display. Each sub-field consists of four periods; a sustain-erasing period, a priming period, an addressing period, and a sustaining period, which are set in sequence.
First, during the sustain-erasing period, a sustain erase pulse Pse-s of negative polarity is applied to the scan electrodes Si. The sustain erase pulse Pse-s of negative polarity has the shape of a sawtooth pulse. This allows the wall charges built up on each electrode by the light emission in the previous sub-field to be erased. At the same time, all the discharge cells in the panel are made uniform irrespective of the presence or absence of light emission in the previous sub-field.
Then, during the priming period, a sawtooth prime pulse Ppr-s is applied to the scan electrodes, while a rectangular prime pulse Ppr-c is applied to the common electrodes. The prime pulse Ppr-s has positive polarity, whereas the prime pulse Ppr-c has negative polarity. The application of the prime pulses Ppr-s and Ppr-c causes a priming discharge to occur in a discharge space near the gap between the scan and common electrodes, thereby generating active particles to facilitate the subsequent writing discharge in the cell. At the same time, this causes wall charges of negative polarity to build up on the scan electrode, wall charges of positive polarity on the common electrode, and wall charges of positive polarity on the data electrode. Subsequently, a charge control pulse Ppe-s is applied to the scan electrode. This causes a weak discharge to occur to reduce the wall charges of negative polarity built up on the scan electrode, the wall charges of positive polarity on the common electrode, and the wall charges of positive polarity on the data electrode.
During the subsequent addressing period, a light-emitting discharge cell is selected. A writing discharge occurs only in the cell selected by the scan pulse Psc-s of negative polarity applied to the scan electrode and the data pulse Pd of positive polarity applied to the data electrode. Wall charges build up on the electrodes of the discharge cell located at the site where light is to be emitted during the subsequent sustaining period. The occurrence of the writing discharge causes wall charges to build up in the discharge cell. In contrast to this, discharge cells in which no writing discharge has occurred still remain unchanged with less wall charges left after having been erased. Such a writing discharge is to occur when the scan and data pulses overlap with each other. As shown in FIG. 4, it requires some time for the writing discharge to occur from the time of application of the pulses. This time is called a “writing discharge delay time (Tw), which is used to determine a scan pulse width Wsc and data pulse width Wd.
A gas discharge occurs as follows. First, an external voltage is applied to cause space charges such as electrons and ions present in the discharge space to move through the gap between the electrodes. Then, the ions collide with the electrodes to generate secondary electrons, which in turn collide successively with gas atoms or molecules in the discharge gas. Thus, secondary electrons are increased exponentially and the gas atoms collided therewith are excited, thereby generating the gas discharge. Therefore, the time required for the generation of a discharge is divided into two periods. A first period is time Ts during which the external voltage is applied to cause space charges such as electrons and ions present in the discharge space to move through the gap between the electrodes to collide with the electrodes. The second period is time Tf during which the ions having collided with the electrodes collide successively with the gas atoms or molecules in the discharge space to cause secondary electrons to exponentially increase and the gas atoms having collided with the ions to be excited. Of these periods, the latter time Tf is referred to as the formation delay time, which is determined by the kind and pressure of the gas, the applied voltage, the cell structure and the like, and has a certain definite value under a constant condition. On the other hand, the former time Ts is referred to as the statistical delay time, which takes on values that vary depending on the amount of excited molecules and atoms present in the space, the amount of the wall charges built up near the electrodes in the discharge cell, and the level of easiness of the emission of secondary electrons from a MgO protective layer formed on the electrodes. That is, the writing discharge delay time Tw is expressed by Tw=Tf+Ts. The relation of (Wsc, Wd)≧Ts+Tf has to be satisfied, where Wsc is the scan pulse width and Wd is the data pulse width, which are necessary to positively generate a writing discharge and thereby form wall charges. The statistical delay time Ts is strongly affected by the excited molecules and atoms present in the discharge space and decreases with increase in number of excited molecules and atoms present in the discharge space.
In this context, the scan pulse width Wsc and the data pulse width Wd were determined in consideration of the priming effect provided by a priming discharge. In addition, a longer period of time from the end of the priming period to a write operation would cause the priming effect to be weakened and the writing discharge delay time to become longer. Thus, there is such a method available that allows the scan and data pulse widths Wsc, Wd to be made longer according to the time elapsed from the end of the priming period (Japanese Patent No. 2737697).
The sustaining period subsequent to an addressing period is a period for display emission, during which a pulse application is initiated from the common electrode and then is followed by alternate applications of negative sustain pulses Ps-s and Ps-c to the scan and common electrodes, respectively. During this period, since a fairly small amount of wall charges is built up in the discharge cells where no write operation was carried out during the addressing period, the application of a sustain pulse to the discharge cells would result in no sustain discharge. On the other hand, in the discharge cells where the writing discharge was generated during the addressing period, positive charges are built up on the scan electrode and negative charges on the common electrode. This causes that the negative sustain pulse voltage applied to the common electrode and the wall charge voltage are superimposed on each other to cause the voltage between the electrodes to exceed the discharge initiation voltage, thereby generating a discharge.
Once a discharge is generated, wall charges are built up so as to cancel out the voltage applied to each of the electrodes. Therefore, negative charges are built up on the common electrode and positive charges are built up on the scan electrode. In addition, the subsequent sustain pulse has a positive voltage on the side of the scan electrode and is superimposed on the wall charge voltage to provide an effective voltage applied to the discharge space that exceeds the discharge initiation voltage, thereby generating a discharge. Hereinafter, the same process is repeated to sustain the discharge. Luminance is determined by the number of times of discharge.
FIG. 5 is a block diagram illustrating a driving circuit employed by a conventional plasma display. In addition, FIG. 6A is a diagram illustrating a driving circuit for the scan electrodes 103; FIG. 6B is a diagram illustrating a driving circuit for the common electrodes 104; and FIG. 6C is a diagram illustrating a data electrode driver 28.
On the horizontal end portions of the conventional plasma display panel, there are provided outlet portions, each on one end, for the scan electrodes 103 and the common electrodes 104 to be taken out therefrom, the driving circuits being connected to the outlet portions.
As a driving circuit for the scan electrodes 103, there is provided a scan pulse driver 21 for outputting a scan pulse to each of the scan electrodes 103. In addition, connected to the scan pulse driver 21 are a priming driver 22 for outputting prime pulses, a sustaining driver 23 for outputting sustain pulses, an erasing driver 24 for applying erase pulses, a scan base driver 25 for outputting scan base pulses, and a scan voltage driver 26 for outputting a scan voltage. Each of the drivers 21–26 constitutes a scan electrode driver 30 for driving the scan electrodes 103.
On the other hand, as a driving circuit for the common electrodes 104, there is provided a sustaining driver 27 for applying sustain pulses to all the common electrodes 104. Only the sustaining driver 27 constitutes a common electrode driver 31 for driving the common electrodes 104.
Furthermore, on a vertical end of the conventional plasma display panel, there is provided an outlet portion for the data electrodes 107 to be taken out therefrom, and the data electrode driver 28 is connected to the outlet portion as a driving circuit.
In addition, there is provided a drive controller 29 for switching the operation of each of the drivers in accordance with an image signal.
Incidentally, in FIGS. 6A to 6C, each driver is represented by a switch. However, the drivers may be constituted by physical switches or by devices such as the bipolar transistor or field effect transistor (FET).
One frame is divided into a plurality of sub-fields and a different number of sustain pulses are provided for each of the sub-fields. The sub-fields are then combined to express gradation. Therefore, the ratio of the numbers of the sustain pulses provided for each sub-field may be determined, for example, such that 1:2:4:8:16:32:64:128, thereby making it possible to express 256 (=28) levels of gradation.
In addition, a large image display area and a high average luminance level would significantly increase power consumption. In this context, a control method for preventing an increase in power consumption is employed. The control method is referred to as the PLE (Peak Luminance Enhancement). FIG. 7 is a circuit diagram illustrating a conventional plasma display employing a PLE control.
An image signal 55 inputted to the plasma display is converted with an image signal processing circuit 56 and a sub-field (SF) controller 57 to a signal for use with the plasma display.
The signal thus converted is inputted to an input signal average luminance level computing circuit 59 to compute the luminance level of the whole screen. Suppose that the average luminance level of the input signal is low (APL: low) or the display area is narrow. In this case, based on the results of the computation, a sustain pulse number controller 58 increases the number of sustain pulses to increase luminance. On the contrary, when the average luminance level is high (APL: high) or the display area is wide, the number of sustain pulses is decreased to limit the luminance. Consequently, the number of sustain pulses in each sub-field is controlled in each frame so as to provide a high peak luminance level on the large display area while an increase in power consumption is being prevented. An image processing portion 60 comprises the image signal processing circuit 56, the SF controller 57, the input signal average luminance level computing circuit 59, and the sustain pulse number controller 58.
Output signals from the SF controller 57 and the sustain pulse number controller 58 are inputted to the drive controller 29 to control the operation of the scan electrode driver 30, the common electrode driver 31, and the data electrode driver 28, which are connected to the scan electrodes, the common electrodes, and the data electrodes of a plasma display panel 51, respectively.
However, the aforementioned conventional driving method for an plasma display provides the total length of time of addressing periods in one frame equal to “the width of a scan pulse×the number of scan lines×the number of sub-fields”, while the addressing period does not contribute to the display light emission. Suppose the length of the addressing period is increased and the number of sub-fields is increased to provide display with an increased number of gradation levels or the number of scan lines is increased to cope with higher resolution. This causes such a problem that a decrease in time to be assigned to the sustaining period in a frame will not provide for sufficient luminance. Furthermore, in some cases, reducing the width of the scan pulse to ensure the sustaining period may cause a reduction in probability of occurrence of a writing discharge, thereby leading to a problem such as a writing failure.